Communication between components on a host platform is necessary for operation of an electronic device. However, communication involves the use of output line or transmission line drivers, which consumes a significant amount of total power used within electronic devices. For example, the communication between the processor and memory, between a memory controller and the processor, between a memory controller and a memory device, between a peripheral controller and a processor or memory subsystem, or other communication, consumes significant amounts of power. In general, the communication among different components can be referred to as I/O (input/output), and is frequently governed by standards (e.g., between components of a memory subsystem). The I/O standards can relate to performance characteristics for I/O power, I/O latency, and I/O frequency. The standards or nominal values of I/O performance settings are set to values that can be achieved across different systems for compatibility and interoperability.
FIG. 1A is a block diagram of a known CMOS output driver. The known CMOS (complementary metal-oxide semiconductor) output driver 134 is a common design for I/O systems. System 102 includes transmitter 110, which communicates with receiver 120. It will be understood that transmitter 110 will be a receiving device when receiver 120 drives communication to transmitter 110. Thus, the roles of transmitting device and receiving device can be reversed, and output driver 134 is illustrated as part of transceiver 130. However, for purposes of discussion herein, the primary focus is on transmission of the signal rather than reception of the signal. For purposes of transmission of a signal from transmitter 110 to receiver 120, receiver 120 can be modeled as a load impedance R122. Transmitter 110 drives transmission line 154 for receiver 120 to receive, by pulling transmission line 154 up to VDD via pull-up (PU) element 140, and pulling transmission line 154 down to VSS via pull-down (PD) element 142. Output impedance R146 is typically matched to the impedance of pad 152 and transmission line 154 as seen by driver 134. Predriver 132 provides signaling and control to driver 134 to output a signal on transmission line 154. Pad 152 interfaces transmitter device 110 to transmission line 154.
An example of use of system 102 is for a driver in LPDDR3 (low power dual data rate version 3, initial specification published in May 2012 by JEDEC). System 102 results in a full swing of the output voltage to drive an output signal. Components other than those of memory subsystems can also use a driver that results in a full swing of the output voltage. The full swing of the output voltage uses a significant amount of power for I/O (input/output) or interfacing between components.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.